比利时专利BE1021245B1 PIXEL WITH LIMITED 1 / F NOISE

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专利摘要:
Pixel with limited 1 / f noise. A pixel is provided which includes at least one transistor. The pixel is arranged to cycle the at least one transistor between two or more set states, e.g., inversion and accumulation, during a readout phase. By running a cycle between the at least two setting states, the time correlation of the 1 / f noise of the read signals is broken; consequently, taking multiple samples and performing an operator on these samples can reduce the effect of the 1 / f noise to an arbitrarily low level.
公开号:BE1021245B1
申请号:E2011/0253
申请日:2011-04-29
公开日:2015-09-22
发明作者:Bart Dierickx
申请人:Bart Dierickx；Caeleste Cvba；Caeleste C.V.B.A.；
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专利说明:

Pixel with limited 1 / f noise. Scope of the invention
The present invention generally relates to image detection, in particular in the field of detection of low-intensity images, such as astronomy and various fields of scientific imaging. However, many other domains of imaging may also benefit from the invention, including, but not limited to, medical imaging, automotive imaging, machine imaging, night vision, digital photography, and digital camcorder image sensors. The present invention relates to a pixel with limited 1 / f noise, an image sensor with a plurality of such pixels, and a method of operating them.
BACKGROUND OF THE INVENTION
Image noise is the random variation of brightness or color information in images generated by the sensor and circuits of an image sensor, and is an undesirable by-product of image capture. Many image sensor technologies have been or are being applied to low-noise imaging. The following list is an example, but is not intended to be an exhaustive list.
Charge-coupled image sensors (CCDs) are still considered today to be highly developed in the field of low-noise imaging. Proof of this is that many, if not all, high-performance astronomical, space and scientific image sensors in the visible area are CCDs. The key to the operation with the lowest readout noise is the correlated double sampling (CDS). Furthermore, CCDs have an inherited low dark current that can even be improved by functions such as "inversion mode". CCDs show a high quantum efficiency (QE), usually higher than 50%, which can even be brought to almost 100% by thinning the back and by lighting along the back.
A variation on CCD is a charge injection instrument, where a charge packet is moved under multiple electrodes and read out in a repetitive and non-destructive manner, using a floating gate readout to over-sample and reduce readout noise.
Over time, CMOS image sensors have gradually taken over the areas where CCDs were superior. Since CMOS can also utilize correlated double sampling (CDS), CMOS sensors were reported with noise performance close to that of CCDs, with an equivalent noise charge (On) as low as 1 to 2 electronRMs · Also CMOS can be combined with the diluting the rear and with lighting along the rear, resulting in a very high quantum efficiency (QE). US7432968 describes a CMOS image sensor that has multiple pixels, each pixel comprising multiple transistors. The image sensor comprises a control unit for controlling the operation of the multiple pixels. The control unit is configured to bring at least one of the transistors in each pixel circuit into an accumulation mode during an integration phase, and then to bring it from the accumulation mode into a strong inversion mode during a readout phase, whereby the 1 / f noise from the pixels is limited.
There is room for pixels and image sensors with an even lower 1 / f noise level.
Summary of the invention
It is an object of embodiments of the present invention to provide a good method and device suitable for use in low radiation intensity imaging, e.g. low light conditions such as, for example, night vision, fast shutter speeds, but also detecting charges that are not come from irradiation.
The above object is achieved by a method and device according to embodiments of the present invention.
In a first aspect, the present invention provides a pixel with at least one transistor, the pixel being adapted to cause the at least one transistor to cycle through two or more setting states during a read-out phase.
The read phase can be a read phase to read a first signal level of the pixel, e.g. a "reset level" or a read phase to read a second signal level of the pixel, e.g. "actual signal level" . The pixel may be arranged to determine the first and / or second signal level by determining multiple readings of that signal level in which a cycle between at least two setting states takes place, and applying an operator to the multiple measurements, such as (but not limited to) averaging the samples. By performing a cycle between the at least two setting states, the temporal correlation of the 1 / f noise of the signals is broken, whereby taking several samples of the same signal level, e.g. reset level or actual signal level, and applying an operator to the samples can limit the effect of the 1 / f noise to an arbitrarily low level.
The pixel may be arranged to have the at least one transistor perform a cycle at least once or twice during a readout phase between two or more setting states, but it is clear that, to have a great effect, the number of cycles back and forth must be large enough. A few tens to a few hundred cycles between the at least two setting states are reasonable values.
It is an advantage of a pixel according to embodiments of the present invention that the 1 / f noise levels thereof are considerably limited relative to the noise levels of pixels according to the prior art and methods for putting them into operation.
In a pixel according to embodiments of the present invention, the at least one transistor adapted to perform a cycle between two or more setting states during a read-out phase may be a MOSFET that is part of an amplifier circuit or of a buffer configuration.
A particular pixel according to embodiments of the present invention can be arranged to have the at least one transistor perform a cycle between inversion mode and accumulation mode.
A pixel according to embodiments of the present invention may be arranged to cause the at least one transistor to cycle between two or more setting states by modulating the potential of the bulk of the at least one transistor. Alternatively, a pixel according to embodiments of the present invention may be arranged to cause the at least one transistor to cycle between two or more setting states by modulating the potential of the gate of the at least one transistor. In still other embodiments of the present invention, a pixel may be arranged to cause the at least one transistor to cycle between two or more setting states by modulating a source and / or drain potential of the at least one transistor.
A pixel according to embodiments of the present invention may comprise multiple transistors, e.g. MOSFETs, wherein all the transistors of the pixel are of the same type, e.g. n-type or p-type, e.g. nMOSFET or pMOSFET. Alternatively, a pixel according to embodiments of the present invention may comprise multiple transistors, e.g. MOSFETs, wherein the transistors of the pixel are of different types, e.g. the pixel may comprise a mixture of n-type and p-type transistors, e.g. mix of nMOSFET and pMOSFET.
A pixel according to embodiments of the present invention may comprise a plurality of transistors, transistors of the same type being provided in the same substrate. Alternatively, transistors of the same type can be provided in separate substrates.
In a pixel according to embodiments of the present invention, transistors of the same type or transistors of different types can be provided in galvanically isolated substrates. The substrates can be galvanically separated by any of an inversely polarized junction, a dielectric layer e.g. in SOI, a physical separation, e.g. air or vacuum. The pixel can be executed in a hybrid or semi-hybrid arrangement.
A pixel according to embodiments of the present invention may comprise a photoreceptor, the photoreceptor having a potential gradient to a location adapted to collect charges. In embodiments of the present invention, the potential gradient can be realized by a continuous or stepwise change in the photoreceptor doping profile. In alternative embodiments, the potential gradient can be realized by a continuous or stepwise change in doping profile of an anchoring layer that anchors the photoreceptor. In still other embodiments, the potential gradient can be realized by a continuous or stepwise change in doping profile of the substrate in which the photoreceptor is placed.
In a second aspect, the present invention provides a matrix of pixels comprising a plurality of pixels according to embodiments of the first aspect.
In a third aspect, the present invention provides an image sensor that includes at least one pixel as in embodiments of the first aspect of the present invention, or a matrix of pixels as in embodiments of the second aspect of the present invention.
An image sensor according to embodiments of the present invention may further comprise a control unit adapted to cause the at least one transistor to perform a cycle between two or more setting states.
An image sensor according to embodiments of the present invention may further comprise circuits adapted to perform an operator on pixel samples after each cycle or after a set of cycles of the at least one transistor between two or more setting states. The operator can be a mathematician or an electrical operator. For example, the operator may be one of the following, but the invention is not limited thereto: average, weighted average, median filtering, low pass filtering, band pass filtering, Kalman filtering, differentiating. The operator can be applied in the digital or in the analog domain.
In a fourth aspect, the present invention provides a circuit for reading a pixel or group of pixels comprising at least one transistor. The read circuit is arranged to cause the at least one transistor to perform a cycle between two or more setting states during a read phase. Such a read circuit according to embodiments of the present invention can be used when the read circuit is not present in the pixel, but is common to many or even all of the pixels.
In embodiments of the present invention, the circuit may be arranged to cause the at least one transistor to perform a cycle between at least inversion and accumulation. In embodiments of the present invention, the circuit may be arranged to cause the at least one transistor to cycle between two or more setting states by modulating the potential of the bulk of the at least one transistor.
In a fifth aspect, the present invention provides a method for operating a pixel comprising at least one transistor. The method comprises, during a readout phase, having the at least one transistor perform a cycle between two or more setting states. In certain embodiments, having the at least one transistor perform a cycle between two or more setting states that the at least one transistor performs a cycle between at least inversion and accumulation.
In embodiments according to the fifth aspect of the present invention, having a cycle run through the at least one transistor between two or more setting states may include modulating a potential of the bulk of the at least one transistor. In alternative embodiments, having a cycle run through the at least one transistor between two or more setting states may include modulating a gate potential of the at least one transistor. In yet other embodiments, having a cycle run through the at least one transistor between two or more setting states may include modulating a source and / or drain potential of the at least one transistor.
A method according to embodiments of the present invention may include collecting multiple pixel samples during the read-out phase, between having the at least one transistor perform a cycle between two or more setting states, and performing a further operator, e.g. averaging , low pass filtering, band pass filtering, median filtering, Kalman filtering, etc ... on the multiple pixel samples.
In a sixth aspect, the present invention provides a method for processing a signal from a pixel or a matrix of pixels for measuring electromagnetic radiation or particle radiation, the method comprising reducing the effective read noise by replacing each signal value by a quantized signal value. By doing this, the signal from the pixel or the matrix of pixels can have a reading noise of considerably less than 1 electronRMS. Replacement of the signal with a quantized signal can be performed on the chip on which the pixel (s) are present, or externally to that chip.
Particular and preferred aspects of the invention are included in the accompanying independent and dependent claims. Features of the dependent claims can be combined with features of the independent claims and with features of other dependent claims as appropriate, and not only as explicitly set out in the claims.
For the purpose of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. It is, of course, understood that not all of these objectives or advantages can be achieved in accordance with any embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention can be embodied or implemented in a manner that achieves one advantage or group of benefits as taught herein, without necessarily achieving other objectives or benefits that can be learned or suggested herein.
BRIEF DESCRIPTION OF THE FIGURES FIG. 1 shows a first example of a pixel capable of carrying out the present invention, the gain transistor being implemented as a source follower. FIG. 2 shows a second example of a pixel capable of carrying out the present invention, wherein the gain transistor is implemented as an inverter with inverting feedback. FIG. 3 and FIG. 4 illustrate examples of pixels that can be driven in accordance with embodiments of the present invention, wherein the MOSFET of the amplifier (which is a source follower in both proposed cases) is pulsed from inversion to accumulation by capacitive coupling of the gate via a capacitor Cc . FIG. 5, FIG. 6 and FIG. 7 illustrate possible sections of a pixel as illustrated in FIG. 2. FIG. 8 illustrates an anchored photo diode implemented in a 3T pixel as can be used in accordance with embodiments of the present invention. FIG. 9 illustrates linear diffusion length as a function of diffusion time, for electrons in bulk silicon, at 300K. FIG. 10 illustrates a first embodiment of a pixel with lateral potential gradient (or depletion stress gradient) wherein the gradient is caused by multiple p-implants of different concentration and / or depth. FIG. 11 illustrates a top view of a possible design of the pixel shown in FIG. 10, showing how different p-implants can overlap. FIG. 12 illustrates a second embodiment of a pixel with a lateral potential gradient (or depletion voltage gradient) wherein the gradient is caused by multiple n-implants of different concentration and / or depth. FIG. 13 illustrates a third embodiment of a pixel with a lateral potential gradient (or depletion voltage gradient) wherein the gradient is caused by multiple concentration zones in the p substrate. FIG. 14 illustrates signal and noise graphs upon control of prior art pixels, in the illustrated case the pixels shown in FIG. 2. FIG. 15 illustrates signal and noise graphs when driving pixels in accordance with embodiments of the present invention, in the illustrated case driving a pixel as shown in FIG. 2, by pulsing a well connection from the amplifier MOSFET. FIG. 16, FIG. 17 and FIG. 18 show simulations of 50 consecutive "readings" taken from a pixel according to a method according to an embodiment of the present invention, wherein the resulting readings are resampled, e.g. rounded to the nearest integer number of electrons. FIG. 16 illustrates a case where the noise is 1 electronRMs, FIG. 17 illustrates a case where the noise is 0.25 electronRMS, and FIG. 18 illustrates a case where the noise is 0.1 electronRMS. FIG. 19 illustrates a probability distribution (normalized to maximum 1) for reading a fixed signal with a standard deviation sigma of 0.25 electronRMS, and thus corresponding to FIG. 17. FIG. 20 shows a graph with the noise of a pixel readout on the X-axis assuming that the noise on a readout has a Gaussian distribution with a certain standard deviation expressed in electronRMS, and with the RMS on the Y-axis standard deviation of the resampled signal also expressed in electronRMS.
The figures are only schematic and not restrictive. In the figures, the dimensions of some elements can be exaggerated and not drawn to scale for illustrative purposes.
In the various figures, the same reference characters refer to the same or similar elements.
Each reference sign in the claims should not be construed as a limitation of the scope.
Detailed Description of Illustrative Embodiments One type of image sensor is an active pixel sensor (APS). APS image sensors are usually made using Metal Oxide Semiconductor (MOS) process technology, in particular, for example, Complementary Metal Oxide Semiconductor (CMOS) process technology, and are usually referred to as (C) MOS image sensors. CMOS image sensors measure light by converting incident radiation (photons) into electronic charge (electrons) via the photoelectric effect. CMOS image sensors usually contain a photoreceptor (e.g., a photodiode) and several CMOS transistors for each pixel.
Existing CMOS image sensors include, but are not limited to, three-transistor (3T) and four-transistor (4T) pixel implementations. Pixel implementations with more than four transistors were also realized.
Pixels not intended for the detection of radiation (electromagnetic radiation or particles) but for the detection of charges (electrons, holes, protons, ions, etc.) form another type of sensors, such as, for example, chemical sensors, biochemical sensors, pressure sensors, temperature sensors, sensors for measuring an electric field or a magnetic field, or any other sensor for measuring other physical quantities that deliver charges.
Hybrid pixels were also considered. CCD-CMOS pixels were also considered. Such pixels have a short portion of a CCD within the pixels, followed by a MOSSFET readout circuit. CCDs were also considered as such, where the CCD comprises several pixels, and where the CCD is read out via one or more MOSFET-based output circuits. The pixel (and output) circuits in these image sensors usually contain a source follower transistor that is used to buffer the photoreceptor or "floating diffusion" voltage on a column line. In CMOS image sensors with 4T anchored photodiode pixel implementations, readout noise is often dominated by the 1 / f noise of the source follower transistor. 1 / f noise, also referred to as flicker noise, has a spectral density that is inversely proportional to the frequency f. The 1 / f noise of the source follower transistor is also a factor in 3T pixel implementations, although there the 1 / f noise is not typically dominant. On the contrary, in 3T embodiments, the readout noise is often dominated by "kTC" noise, which is the noise associated with resetting the pixel to a reset level. Nevertheless, the 1 / f noise of a source follower transistor also makes a significant contribution to the total noise in 3T pixel implementations.
The generally accepted physical explanation for 1 / f noise in MOSFETs is the McWorther theory. McWorther explains the fluctuations in the MOSFET current as induced by coulomb states (a coulomb state is nothing but a positive or negative electrical point charge) in the vicinity of the interface between a semiconductor material and an insulating layer, e.g. an SiO2-Si interface . The coulomb states can change state by catching or releasing cargo carriers. The presence of the coulomb is at the interface and influences the inversion layer and thus the amount of current flowing through the transistor. The capture and release modulates the MOSFET current over time.
Since the time constants involved in this capture and / or release of charges vary from very long times (minutes, even hours) to very short times (less than nanoseconds), the spectrum of the resulting noise typically has a specific character, with the spectral The noise density is proportional to l / frequency, where α is usually close to 1, resulting in the name "1 / f noise".
When only one such interface state is active in the MOSFET at a certain operating point, one can actually observe the capture / release of charge carriers. The current has two levels, hence the nickname "Aselect Telegraaf Signal" (RTS) noise. The RTS spectrum is not 1 / f, but has a so-called "Lorentian spectrum". Since the superposition of many RTSs is the same as 1 / f noise, the superposition of many Lorentian spectra results in the expected 1 / frequency spectrum. An extensive theory and experimental testing of RTS noise and 1 / f noise in MOSFETs can be found in the following article, which is incorporated herein by its reference: MJ.Kirton and MJ.Uren, "Noise in solid-state microstructures: A new perspective in individual defects, interface States and low-frequency (1 / f) noise ", Advances in Physics, 1989, Vol.39 No.4, p.367-468.
According to embodiments of the present invention, pixels are generated in which the sources of 1 / f noise are reduced or completely removed. Such pixels comprise at least one transistor, for example a MOSFET, and a control unit. If the pixel comprises multiple transistors, then the transistor, e.g. MOSFET, which generates the most 1 / f noise according to embodiments of the present invention is arranged to cycle through a cycle between two or more setting states during a read-out phase.
Examples of such pixels are illustrated in FIG. 1 and FIG. 2. Both figures illustrate 4T pixels, although the invention is not limited thereto and can also be implemented in 3T pixels or other forms of pixels comprising at least one transistor. In the pixels illustrated in FIG. 1 and FIG. 2, both transistors of a first type and transistors of a second type, respectively, are provided, e.g. nMOSFETs and pMOSFETs, which can be controlled separately as illustrated below. FIG. 1 is a schematic representation of a four-transistor (4T) pixel 10 for a CMOS image sensor according to a first embodiment of the present invention. All transistors in the pixel are MOS transistors. The pixel 10 comprises a photoreceptor 11 for converting incident radiation to electronic charge. The pixel 10 further comprises a sampling and holding transistor 12, a reset transistor 13, a source follower transistor 14 and a column selection transistor 15. Transistors 12 and 13 are shown as transistors of a first type, in the illustrated embodiment nMOS transistors while transistors 14 and 15 are shown as transistors of a second type, in the illustrated embodiment pMOS transistors.
The photoreceptor 11 is connected between the ground and the source of the transistor 12 for sampling and retention. The gate of the sampling and retaining transistor 12 is connected to a transfer line 16, and the drain of the sampling and retaining transistor 12 is connected to the source of the reset transistor 13 and to the well of the source follower transistor 14. The drain of the reset transistor 13 is connected to the line of the supply voltage vdd. The gate of the reset transistor 13 is connected to a reset line 17. The source of the source follower transistor 14 is connected to a supply voltage line vss. The drain of the source follower transistor 14 is connected to the source of the column selection transistor 15. The gate of the column selection transistor 15 is connected to a selection line 18. The drain of the column selection transistor 15 is connected to a column output line 19. In the illustrated embodiment, the bulk of the transistors 12, 13 and 15 is connected to the ground, while the bulk of the transistor 14 is connected to a well potential (a well is an area with another bulk doping). For this, the source follower transistor 14 is provided in a well, as illustrated in FIG. 7, FIG. 8 and FIG. 9 and discussed below. In this way, the source follower transistor 14 can be driven separately from the other MOSFETs.
Reset transistor 13 is used to reset the voltage on the photoreceptor 11. The sampling and retention transistor 12 is used to sense and buffer the photoreceptor voltage. Source follower transistor 14 receives and amplifies the signal from transistor 12 for sampling and retention. Column selection transistor 15 is used to select pixel 10 for reading.
Pixel information from a CMOS image sensor is typically sampled row by row. To select a row of pixels, the selection line 18 for the selected row of pixels 10 is set to high. Since in the illustrated embodiment the column selection transistor 15 is a pMOS transistor, the inverse of the high signal on the selection line triggers the transistor to turn on.
Pixel information for pixel 10 is typically generated and sampled in three phases; a pixel reset phase, an integration phase and a readout phase.
During the reset phase, pixel 10 is reset by setting the reset line 17 and the transfer line 16 high (e.g., above vdd). The high setting of the reset line 17 turns on the reset of the transistor 13, and the high setting of the transfer line 16 turns on the sampling and retention transistor 12, and this sets the voltage across the photoreceptor 11 to a fixed start value.
The reset line 17 and the transfer line 16 are then set to a low value (e.g. connected to the ground), whereby the reset transistor 13 and the transistor 12 for sampling and retention are turned off, and the integration phase is started. While the reset line 17 and the transfer line 16 are at a low value, pixel 10 integrates the amount of radiation incident on the photoreceptor 11, and the photoreceptor 11 discharges from the reset level downwards. At the end of the integration phase, the transfer line 16 is set to a high value to start the read phase. Setting the transmission line 16 to a high value turns on the sampling and retention transistor 12, and ensures that the charge present on the photoreceptor 11 is transferred to the parasitic capacitance at the node connected to the source of the source follower transistor 13. The transfer line 16 is then set to a low value, whereby the sampling and retention transistor 12 is turned off.
For reading, the selection line 18 is set to a high value, whereby a low signal is applied to the gate of the column selection transistor 15. Setting the selection line 18 to a high value, or thus applying a low value signal to the gate of the column selection transistor 15, turns on the latter transistor and brings the integrated voltage to the column output line 19, on condition that that the source follower transistor 14 is conducting.
During the readout phase, the reset voltage and the integrated voltage are usually both successively read out from the column output line 19. The image signal generated by each pixel 10 is usually the difference between the readout reset voltage and the voltage on the photoreceptor 11 after the integration period ( ie the integrated voltage).
According to embodiments of the present invention, the effect of the 1 / f noise is reduced by the MOSFET responsible for the 1 / f noise, in the illustrated embodiment repeatedly pulsing the source follower transistor 14 from a first state to a second state , e.g. from inversion to accumulation and back, and by oversampling its signal, and all this during the same readout phase. The source follower transistor 14 can be brought into accumulation mode by providing voltages such that the gate voltage minus the bulk voltage is less than the threshold voltage for that transistor 14. The source follower transistor 14 can be brought into strong inversion mode by providing voltages such that the gate voltage minus the source voltage is greater than the threshold voltage for that transistor 14. The provision of such voltages, in the embodiment illustrated in FIG. 1, can be obtained by repeatedly pulsing the bulk voltage so that the above requirements for accumulation mode resp. strong inversion mode. FIG. 2 also illustrates a 4T pixel 20. The same elements as in FIG. 1 have the same reference number. Again, all the transistors in the pixel are MOS transistors. A difference from FIG. 1 is that an amplifier 22 with inverting feedback is provided as the amplification transistor. The inverting feedback amplifier 22 is, in the illustrated embodiment, a pMOS transistor. The source of the inverting feedback transistor 22 is coupled to a power source vpix. The drain of the inverting feedback amplifier 22 is coupled to a drain of an nMOS column selection amplifier 23. The gate of the inverting feedback amplifier 22 is coupled to the drain of the transistor 12 for sampling and retention. A reset transistor 24 is provided which is connected in a different way in the pixel 20: the reset transistor 24 is, in the illustrated embodiment, an nMOS transistor, the source of which is electrically connected to the drain of the amplifier 22 with inverting feedback, while the drain of the reset transistor 24 is connected to the gate of the inverter 22 with inverting feedback. The gate of the reset transistor 24 is connected to a reset line 25. In this embodiment, as indicated above, the column selection transistor 23 is also an nMOS transistor. The gate of the column selection transistor 23 is connected to a selection line 26. The source of the column selection transistor 23 is connected to a column output line 19 and the drain of the column selection transistor 23 is connected to the drain of the amplifier 22 with inverting feedback.
The configuration of FIG. 2 is a type of capacitive feedback charge amplifier or charge transimpedance amplifier (CTIA), the charge to voltage conversion of which is input by a feedback capacity, which in the illustrated case is the gate-drain capacity of the inverting feedback amplifier 22. It is clear to a person skilled in the art that the pixel can be operated with a higher charge to voltage conversion than the circuit in FIG. 1.
Also in this embodiment, the MOSFET amplifier 22 with inverting feedback can be driven separately from the other MOSFETs in the pixel circuit. The inverting feedback amplifier 22 can be repeatedly switched from a first state to a second state, e.g. from inversion to accumulation, and back, and its signal can be over-sampled. The inverting feedback amplifier 22 can be brought into accumulation mode by applying voltages such that the gate voltage minus the bulk voltage is less than the threshold voltage for that transistor 22. The inverting feedback amplifier 22 can be brought into a strong inversion mode by voltages so that the gate voltage minus the source voltage is greater than the threshold voltage for that transistor 22. The provision of these voltages, in the embodiment shown in FIG. 2, can be obtained by repeatedly pulsing the bulk voltage so that the above requirements for accumulation mode resp. strong inversion mode can be achieved.
When the interface states in MOSFETS perform a cycle between different setting states (such as, for example, between accumulation mode and inversion mode), they are forced to fill or empty their states much quicker than when left to normal operation with few changes in setting states . The present inventor has found that, by doing so, the long time correlation of the charge state is broken. By removing the long time correlation, the noise spectrum loses its dominant low frequency components and becomes "white noise." It is well known to specialists in the field that a white noise spectrum and the absence of correlation go hand in hand. Successive samples taken from a signal containing white noise are not correlated; therefore, taking several samples and averaging them will reduce the noise with respect to the signal. The noise reduction is approximately proportional to the square root of the number of samples taken to calculate the average. Since there is no real upper limit on the number of samples taken, with the exception of the time allowed by the application, one can thus limit the effect of the noise to any low level.
For normal MOSFETs, the "useful" setting state is called "inversion" (where a distinction is made between weak and strong inversion). When an nMOSFET is turned on, the positive gate voltage will attract electrons to the SiO2-Si separation branch, the p-type substrate material being "inverted" into an electron-rich "n" layer. Accumulation is a state where the MOSFET is strongly switched off. However, it should be noted that in some types of MOSFETs, such as buried channel MOSFETs, accumulation is the turned on state, and inversion is the turned off state. One can consider many setting states, such as various degrees of weak and strong accumulation or inversion. The state between accumulation and inversion is called the "flat band".
Pixels according to embodiments of the present invention are designed with the possibility in mind that certain MOSFETs pass through a cycle, in particular, for example, amplifying MOSFETs, between at least a first and a second mode, e.g. between inversion and accumulation, corresponding to on and off positions of the MOSFETs. This can be achieved in many ways, a few of which are illustrated in FIG. 1 and FIG. 2, FIG. 3 and FIG. 4, FIG. 5 to FIG. 7.
Various techniques can be used to switch the gain transistor, such as, for example, a source follower transistor or an inverting feedback amplifier, between an accumulation mode and a strong inversion mode in pixels of a CMOS image sensor according to embodiments of the present invention. Such techniques include pulsing the substrate, or pulsing the signal applied to the gate, and these techniques are described in more detail below.
Many classic pixels contain only one type of MOSFETs, typically nMOSFETs. In such pixels, it is difficult to modulate the substrate of one MOSFET as described with respect to embodiments illustrated in FIG. 1 and FIG. 2, since this substrate is common to all MOSFETS, and often is the substrate connection of the photoreceptor. In the embodiments illustrated in FIG. 1 and FIG. 2, modulation of the MOSFETs substrate to cause the MOSFET to cycle through inversion and accumulation is made possible by providing different types of MOSFETs.
In accordance with the embodiments illustrated in FIG. 1 and FIG. 2, cycling through the at least two states can be performed by causing a well in which the amplifier MOSFET 14, 22 is provided to cycle through. For this purpose, a well contact 50 can be provided which can be controlled with suitable signals.
When the substrate of said amplifier MOSFETs is to be isolated from the others, this can be done in various ways, such as, but not limited to:
By a junction, as in FIG. 5 and FIG. 6;
By a dielectric as in FIG. 7, where this is based on an SOI process;
By other means known to those skilled in the art for electrically separating electrical nodes. FIG. 5 illustrates a possible cross section of the pixel of FIG. 2. The illustrated photoreceptor 11 is an anchored photodiode. In the illustrated embodiment, the anchored photodiode is in the same substrate 51 as the MOSFET circuit. As can be seen in the illustrated embodiment, the pMOSFET 22, which is an amplifier MOSFET 22, is provided with an nWELL 52 separated from the other circuits by an inversely polarized junction. FIG. 6 illustrates another possible cross section of the pixel of FIG. 2. The illustrated photoreceptor 11 is an anchored photodiode. In the illustrated embodiment, the anchored photodiode is in the same substrate 51 as the MOSFET circuit. As can be seen in the illustrated embodiment, the pMOSFET 22, which is the amplifier MOSFET 22, is provided with an nWELL 60, thus providing isolation by an inversely polarized junction. In addition, the nWELL 60 of the pMOSFETs is surrounded by a deep P-well or P-tub 61 that creates a potential gradient between the P-tub 61 and the p-substrate 51 that pushes charge carriers, e.g. electrons, away so that the nWELL 60 does not compete or less with the real photo diode 11 to capture photo electrons. FIG.7 illustrates yet another possible cross-section of the pixel of FIG. 2. The illustrated photoreceptor 11 is an anchored photodiode. In the illustrated embodiment, the anchored photodiode 11 is in the same substrate as the MOSFET circuit. The pMOSFET 22, which is the amplifier MOSFET 22, is provided with an nWELL 70 which is isolated from the nMOSFET circuit by means of a dielectric 71 as may have been used in an SOI process.
In the above embodiments, the amplifier MOSFET 22 goes through a cycle between accumulation and inversion modes by causing the substrate 51 to cycle through. In alternative embodiments, the amplifier MOSFET 22 can be run through a cycle between inversion and accumulation by not influencing the substrate 51, but by modulating its gate voltage sufficiently above and below the threshold voltage. This can be done by a suitable circuit, e.g., by a capacitive coupling with the gate voltage, as shown in FIG. 3 and FIG. 4, where FIG. 3 contains only nMOSFETS, and FIG. 4 contains both nMOSFETS and pMOSFETs.
In accordance with the embodiments illustrated in FIG. 3 and FIG. 4 illustrating pixels 30, 40 with a 4T layout such as the pixels illustrated in FIG. 1, cycling through the at least two states can be performed by causing the gate of the amplifier MSOFET 31, 14 to cycle through. A capacitive coupling 32, 42 to these gates can be provided for this purpose. The capacitive coupling 32, 42 provides a means to capacitively influence the gate voltage of the MOSFET 31,14, so that the MOSFET 31,14 can be pulsed from inversion to accumulation and back. This capacitive coupling comprises a capacitor 32, 42 of which a first capacitor plate is electrically connected to the gate of the amplifier MOSFET 31, 14, and of which a second capacitor plate is electrically connected to an electrode on which a PULS signal 33, 43 can be applied.
At the end of the integration phase, charges collected on the photoreceptor 11 are transferred to the capacitor 32, 42. During the readout phase, i.e. after the collected charges have been transferred to the capacitor 32, 42, a pulse signal 33, 43 which repeatedly switches between a high and a low voltage value applied to the second capacitor plate of the capacitor 32, 42. By doing this, the amplifier transistor 31, 14 repeatedly enters an accumulation mode and an inversion mode.
In the production of pixels, for example 4T pixels or 3T pixels or pixels with any other suitable number of transistors, the photoreceptor 11 is often a buried or anchored photodiode. It should be noted that also 3T pixels can use an anchored photo diode 11, as shown in FIG. 8. In such a case, no transfer gate is provided, but a direct connection is made from the gate of the amplifier transistor 80 to the deep implantation of the anchored diode 11. The photoreceptor diode 11 is anchored by an anchoring layer 81 around the photoreceptor diode force collected cargo to the direct link - see FIG. 8.
For large pixels, the time required to transfer the charge, or to collect the charge, becomes critically dependent on the lateral distribution of the photo charge carriers in the anchored diode 11. The time it takes for a free charge carrier to settle in spread linear direction in the absence of an electric field growing by the square of the distance. This relationship obeys
where lD is the diffusion length or diffusion distance, tD the diffusion time, pe the mobility of the free charge carriers, k the Boltzmann constant, t the absolute temperature in degrees Kelvin, and q the charge of a free charge carrier.
Table I shows an estimate of the diffusion time as a function of the diffusion distance, for linear diffusion in silicon, starting from electrons with a mobility in the bulk of 1100 cm 2 / V.s at room temperature (300 K):
This relationship is also shown in FIG. 9. It can be seen that the diffusion time becomes important relative to the readout time of the pixels (where a typical readout time for a row of pixels is in the order of 1 to 10 ps), for large pixels such as those that can be used in accordance with embodiments of the present invention.
In order to speed up the time to collect charges, an internal electric field can be created in the photodiode in various ways. Such methods have, for example, been proposed in the past (such as for example in US6683360 "Multiple or graded epitaxial wafers for partial or radiation detection", incorporated herein by reference in its entirety). Other suitable methods that can be used in conjunction with embodiments of the present invention can be based on the creation of an electric field by providing a lateral impurity doping gradient in the photoreceptor. FIG. 10 and FIG. 11 show how such an impurity or dopant gradient can be achieved by using multiple shallow implantations of an anchored layer to anchor the photoreceptor 11, e.g., by multiple shallow p-type implants 100, 101, 102. Two or two are more adjacent implants, with increasing doping levels, as shown in side view in FIG. 10 or in top view in FIG. 11, or even a gradually increasing dopant implantation (not illustrated). Alternatively, the two or more implants may have different depths. In the embodiment illustrated in FIG. 12, the impurity or doping gradient is achieved by different deep implantations of the photoreceptor layer, e.g., different deep n-type implants 120, 121, 122. Again, there may be two or more adjacent implants with decreasing doping level, as illustrated in FIG. 12, or alternatively a gradual doping profile (not illustrated). Alternatively, the two or more implants may have different depths. In the embodiment illustrated in FIG. 13, this is achieved by means of a multiple or graded dopant concentration 130, 131, 132 in the substrate or epitaxial layer below the anchored photodiode 11.
Methods for realizing these impurity or doping gradients are known to those skilled in the art.
As explained above, a lateral concentration gradient can be applied to the shallow implantation (FIG. 10 and FIG. 11), the deep implantations (FIG. 12) and even the substrate (FIG. 13) of the anchored photodiode.
A pixel according to embodiments of the present invention, as illustrated above, can be used in a method according to embodiments of the present invention. In one embodiment, a method according to embodiments of the present invention comprises operating a pixel by reading it out as usual. The reading of the pixel can, for example in raw mode, simply include reading the signal after the integration of the photo charge, or in double sampling (double sampling - DS) where the reading of a signal level is followed by the reading of the signal a reset level; or in correlated double sampling (correlated double sampling - CDS), where reading the reset level is followed by reading a signal level. The above list of methods for reading a pixel is not exhaustive; other methods of reading a pixel may also apply.
Classically, the readout levels for reset and signal levels are usually single voltage levels ("samples") that are then amplified, differentiated, or buffered to the global output of the image sensor or to an ADC.
In accordance with embodiments of the present invention, multiple samples are taken for the reset and / or signal levels. Taking multiple samples for the same signal is often called "over-sampling", which is classically known as a noise-reducing technique, provided that the multiple samples are then averaged. Such classical over-sampling technique is shown in FIG. 14. FIG. 14 illustrates in a first graph 140 the reset signal, which is applied, for example, to a reset transistor in a 4T pixel. A second graph 141 illustrates the transfer signal applied, for example, to a transistor for sampling and retention in a 4T pixel. The peaks in the graph 140 of the reset signal and in graph 141 illustrating the transfer signal applied to the transistor for sampling and retention define a reset phase 142, during which the photoreceptor 11 is reset to a starting voltage, a first read-out phase 143, during which the reset voltage of the photoreceptor 11 is read, a transfer phase 144, during which charges collected by the photoreceptor 11 are transferred to a memory element, such as, for example, a capacitance or a parasitic capacitance of the amplifying transistor 14, 22, and a second read-out phase 145, during which the voltage level of the charges collected by the photoreceptor 11 is read out. Graph 146 in FIG. 14 illustrates an idealized read signal, i.e. the signal as it would be read on the column line if no noise were present. It can be seen from graph 146 that this includes a first level 147 representing the reset voltage, and a second level 148 representing the signal level. Graph 149 illustrates an example of a corresponding non-ideal signal in which noise is present, with predominantly low frequency (1 / f) noise. It can be seen that the average voltage level of the reset signal and the average voltage level of the signal voltage do not differ that much. The AV signal after CDS suffers from a large component of the low frequency noise.
Inventive in the method according to embodiments of the present invention is that the MOS interface of (one or more) of the MOSFETs of the pixel passes through a cycle, during a readout phase 143, 145, between at least a first and a second state, e.g. between inversion and accumulation, between each or groups of said multiple samples. In this way, the signal is repeatedly sampled and averaged (or an operator equivalent with averaging is applied). This is also called over-sampling. By doing this, as found in accordance with embodiments of the present invention, the multiple samples lose the time correlation caused by the 1 / f or RTS noise. If the over-sampling is followed by an averaging, this will result in a considerable reduction in noise. This is illustrated in FIG. 15, for a pixel as in FIG. 2 wherein the amplifier transistor 22 goes through a cycle between accumulation and inversion by pulsing the connection 50 to the well. The reset phase 142, first read phase 143, transfer phase 144 and second read phase 145 are as in FIG. 14. Chart 150 in FIG. 15 illustrates the level of the reset signal and the timing of its pulses. Graph 151 illustrates the transfer signal applied to the transistor for sampling and retention. In the illustrated embodiment, the pixel traverses a cycle between a first and a second state, e.g., between accumulation and inversion, during reading by applying a suitable voltage to the bulk of the amplifier transistor. This is shown in graph 152 of FIG. 15 suggested. It can be seen that, by doing so, the idealized output signal 153 of the pixel, i.e., the signal without noise, jumps between two values, both during the first readout phase 143 and during the second readout phase 145. One of the extreme values of the read signal during the first readout phase 143, e.g. the maximum value, corresponds to the reset level of the photoreceptor 11. One of the extreme values of the readout signal during the second readout phase 145, e.g. the maximum value , corresponds to the signal value of the photoreceptor 11. Graph 154 of FIG. 15 illustrates an example of a corresponding non-ideal signal in which noise is present. It can be seen that the average extreme value corresponding to the read signal during the first readout phase 143 and the average extreme value corresponding to the readout signal during the second readout phase 145 differ sufficiently to be distinguishable. The signal on the column output line includes the low frequency (1 / f) noise. It can be seen that although the noise is of the same order of magnitude as in FIG. 14, the noise is not correlated with time, so that the average of the over-sampled signal, after CDS, has a reduced noise content, so that AV is smaller.
The multiple samples during one readout phase can be combined into one "readout" by any suitable means, e.g. by averaging, by integration or by any other suitable operator, such as, but not limited to, low pass or band pass filtering, use of filters with finite or infinite impulse response, taking a weighted average, linear or non-linear filtering, median filtering, Kalman filtering.
This can happen in the analog or digital domain. This operation can also be called 'over-sampling'.
Such a reading can also include the effect of the DS or CDS, by making the difference between reading the reset level and reading the signal level. These combinations can occur in various ways in the analog domain or in the digital domain, internally in the chip on which the pixels are present or externally on the chip, as is known to a person skilled in the art.
The obtained "readings" are themselves regarded as pixel signal values.
Methods in accordance with embodiments of the present invention bring the noise from the semiconductor image sensors below the equivalent input noise of 1 electronRMS. Once an image sensor has a read-out noise performance that is sufficiently below 1 electronRMS, a further operator can be used to effectively further reduce the read-out noise. In FIG. 16, FIG. 17, FIG. 18 is a hypothetical sequence of 50 consecutive readings of the signal of a pixel with a certain RMS of readout noise; 1 electronRMS in FIG. 16, 0.25 electronRMS in FIG. 17 and 0.1 electronRMS in FIG. 18, the resulting readings being resampled, i.e., rounded to the nearest whole number of electrons. Here the signal level starts at 0, and increases incrementally after 20 and 40 samples. The readings are subject to a predetermined noise level. When the noise in the readings is sufficiently low, e.g., below the 0.28 noise electron RMS as set forth below, it becomes possible to distinguish steps in the signal corresponding to a signal difference of 1 electron, as shown in FIG. 17 and FIG. 18.
The method is as follows: resample the readings 160,170,180 or round them to their nearest integer number of electrons to form resampled readings 161, 171, 181. It has been found that the RMS of the re-sampled population of readings 161,171,181 is lower than the RMS of the original readings 160,170,180.
This is explained as follows. In FIG. 19, the probability distribution is shown (normalized to maximum 1) for reading a fixed signal with an RMS or standard deviation sigma of 0.25 electron RMS, thus corresponding to FIG. 17. The Gaussian distribution of 0.25 noise electrons is shown around an average "0", see graph 190. Next, each readout 170 in the population is rounded to the nearest integer 171, resulting in a new discrete distribution 191, also illustrated in FIG. 19. The RMS of the new, non-continuous, distribution is less than 0.25.
It appears that it is necessary to start a noise distribution that is already below 0.28 noise electrons in order to achieve a lower noise after resampling. This relationship is shown in FIG. 20, which shows a graph 200 with the X-axis noise of the readout of a pixel assuming that the noise on the readout has a Gaussian distribution with a predetermined standard deviation expressed in electron RMs; and with the Y-axis the RMS or standard deviation of the resampled signal, also expressed in electron RMS. It should be noted that the resampling results in a lower RMS when the noise of the original readout is lower than 0.28 electron RMS. 20 it can be seen that for noise> 0.29 electron RMS there is no effect (rather a limited negative effect). The lower the original noise, the more striking is the improvement; eg for an original noise of 0.1 electron RMs, the noise of the resampled signal falls back by a factor of more than 100 (the resampled signal has a noise of only 0.00076 electron RMs), making this a virtually noise-free system.
Although the invention has been illustrated and described in detail in the drawings and the foregoing description, this illustration and description should be considered as illustrative or exemplary and not restrictive. The invention is not limited to the described embodiments.
For example, the concept of embodiments of the present invention is described above for 4T pixels, but can in fact be applied to all pixels where a MOSFET is an important transistor of an amplifier, where this amplifier can be, for example, a source follower, a single-sided amplifier , a differential amplifier, an operational amplifier, a transimpedance amplifier, a cascode amplifier, a separation amplifier, etc. It should also be noted that SOI-FETs and FINFETs are also essentially MOSFETs, to which embodiments of the present invention can be applied. In fact, instead of MOSFET, one can read "a transistor for which running through a cycle between setting states shortens the time correlation of its temporal (low frequency) noise".
As another example, it is possible to operate the invention in an embodiment in which instead of a 4T pixel a 3T pixel, an anchored photoreceptor pixel or even a hybrid pixel is provided, more generally any form of pixels in which detectors are separated from the integrated readout circuit (ROIC).
Embodiments of the present invention can also be applied to CCDs, where the final stages are based on MOSFETs, or on CCD-CMOS pixels, where parts of the CCD are embedded in pixels or in pixel groups.
Embodiments of the present invention can be applied or imaging under visible light, but also on all other electromagnetic wavelengths and on detection of high energy particles (electron, hadron, ion, ...).
Other variations on the described embodiments can be understood and practiced by those skilled in the art of the claimed invention from a study of the drawings, the description and the appended claims. In the claims, the word "includes" does not exclude other elements or steps, and the indefinite article "a" does not exclude a plurality. The mere fact that certain measures are proposed in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Each reference number in the claims is not to be construed as a limitation of the scope of protection.

权利要求:
Claims (23)
[1]
CONCLUSIONS
A pixel comprising at least one transistor, the pixel being arranged to cause the at least one transistor to cycle through two or more setting states during a read-out phase.
[2]
A pixel according to claim 1, wherein the at least one transistor arranged to pass a cycle between two or more setting states during a read-out phase is a MOSFET that forms part of an amplifier circuit or a buffer configuration.
[3]
3. A pixel according to any one of the preceding claims, wherein the pixel is arranged to cause the at least one transistor to cycle through an inversion mode and an accumulation mode.
[4]
A pixel according to any one of the preceding claims, wherein the pixel is arranged to cause the at least one transistor to cycle through two or more setting states by modulating the potential of the bulk of the at least one transistor.
[5]
A pixel according to any of claims 1 to 3, wherein the pixel is arranged to cause the at least one transistor to cycle through two or more setting states by modulating the potential of the gate of the at least one transistor.
[6]
A pixel according to any of claims 1 to 3, wherein the pixel is arranged to cause the at least one transistor to cycle through two or more setting states by modulating a source and / or drain potential of the at least one transistor.
[7]
A pixel according to any one of the preceding claims comprising a plurality of transistors, wherein at least two transistors are arranged in galvanically isolated substrates.
[8]
A pixel according to claim 7, wherein the substrates are galvanically separated by any of an inversely polarized junction, a dielectric layer, a physical separation.
[9]
A pixel according to any one of the preceding claims comprising a photoreceptor, wherein the photoreceptor has a potential gradient to a location adapted to collect charges.
[10]
A pixel according to claim 9, wherein the potential gradient is realized by a continuous or stepwise change in the doping profile of the photoreceptor.
[11]
A pixel according to claim 9, wherein the potential gradient is realized by a continuous or stepwise change in the doping profile of an anchoring layer that anchors the photoreceptor.
[12]
12. A pixel according to claim 9, wherein the potential gradient is realized by a continuous or stepwise change in the doping profile of the substrate in which the photoreceptor is placed.
[13]
13. - An image sensor comprising at least one pixel as in one of the preceding claims.
[14]
An image sensor according to claim 14, further comprising a control unit adapted to cause the at least one transistor to cycle through two or more setting states.
[15]
An image sensor according to any one of claims 13 or 14, further comprising circuits adapted to perform an operator on pixel samples after each cycle or after a set of cycles of the at least one transistor between two or more setting states.
[16]
16. - A circuit for reading a pixel or group of pixels comprising at least one transistor, the circuit being adapted to cause the at least one transistor to pass through a cycle between two or more setting states during a read-out phase.
[17]
A circuit according to claim 16, wherein the circuit is arranged to cause the at least one transistor to cycle through at least inversion and accumulation.
[18]
A circuit according to any of claims 16 or 17, wherein the circuit is arranged to cause the at least one transistor to cycle through two or more setting states by modulating a bulk potential of the at least one transistor.
[19]
A method of operating a pixel comprising at least one transistor, the method comprising, during a readout phase, passing through the at least one transistor of a cycle between two or more setting states.
[20]
A method according to claim 19, wherein having the at least one transistor perform a cycle between two or more setting states that the at least one transistor performs a cycle between at least inversion and accumulation.
[21]
A method according to any of claims 19 or 20, comprising collecting multiple pixel samples between passing through the at least one transistor of a cycle between two or more setting states, and performing a further operator on the multiple pixel sampling.
[22]
22. - A method for processing a signal from a pixel or a matrix of pixels for measuring electromagnetic radiation or particles, the method comprising reducing the effective read noise by replacing each signal value with a quantized signal value.
[23]
A method according to claim 22, wherein replacing a signal value with a quantized signal value is performed on a chip or externally to the chip.

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